High frequency amplifiers are devices that amplify a high frequency signal and transfer the high frequency signal to a load termination. In high frequency power amplifiers the transfer of the high frequency signal is typically done in successive power amplifier stages, wherein each of the successive power amplifier stages has gradually a larger power capability than a preceding power amplifier stage. The transfer of the high frequency signal through each one of the successive power amplifier stages to the load termination must be carefully designed in order not to attenuate part of the high frequency signal, thereby degrading the high frequency power amplifier performance. Optimization of the transfer of the high frequency signal is achieved by impedance matching. Impedance matching matches a source impedance to a load impedance ensuring maximum transfer of power from the source impedance to the load impedance. Impedance matching is sometimes realized with discrete passive components that offer predetermined high frequency characteristics. Impedance matching is typically performed by impedance matching circuits. An example of impedance matching circuits used in high frequency amplifiers is shown on FIG. 1 of U.S. Pat. No. 7,119,623 B2. A similar figure is shown in FIG. 1a of this document. FIG. 1a shows a MOS device 10 with a gate terminal G, a source terminal S and a drain terminal D and an output capacitance Cout. The output capacitance Cout is a parasitic output capacitance which has a negative effect on the performance of the MOS device 10 by adding a frequency-dependent component to the MOS device's 10 output impedance. The MOS device 10 of FIG. 1a is connected in a common source configuration, that is with the source terminal S connected to a reference potential common to the gate terminal G and to the drain terminal D. The gate terminal G and the drain terminal D are respectively an input and an output for the MOS device 10. The reference potential is a ground reference potential GND. A parasitic inductive path 15 is present between the source terminal S and the ground reference potential GND. The parasitic inductive path 15 may be caused by the presence of a physical distance between the actual source terminal S and the effective location of the ground reference potential GND. An impedance matching circuit is connected to the drain terminal D of the MOS device 10. The impedance matching circuit shown in FIG. 1a includes a shunt inductor L in series with a shunt capacitor C and a series inductor INDS connected between the drain terminal D of the MOS device 10 and a signal output terminal Output. The shunt capacitor C is coupled at one side to a reference potential GNDM which may differ from the ground reference potential GND (e.g. at a different location). The shunt inductor L provides a parallel resonant circuit together with the output capacitance Cout during operation at the high frequency of interest. The output capacitance Cout is therefore effectively compensated by the shunt inductor L. The shunt inductor L is coupled to the reference potential GNDM through the large shunt capacitor C to prevent a DC current through the shunt inductor L to flow to the reference potential GNDM. The parasitic inductive path 15 hampers a proper function of the MOS device 10 during operation at high frequency because it provides an undesired feedback for the high frequency signal from output to input. Further to that, a distance d is present between the two different physical distant points of the reference potential GNDM at which the impedance matching circuit and the MOS device 10 are both connected. The distance d may increase a value of the parasitic inductive path 15. The increase of the value of the parasitic inductive path 15 may increase an influence of the return current 20 flowing from the output of the MOS device 10 to the input of the MOS device 10 passing through the increased parasitic inductive path 15. This return current 20 is depicted in FIG. 1a with a dashed arrow line pointing to the source terminal S of the MOS device 10. One of the problems generated by this increased influence of the return current 20 is for example that stability and gain of the MOS device 10 may be compromised.